US 11,842,685 B2
Pixel and display device including the same
Yong Jae Kim, Yongin-si (KR); In Jun Bae, Yongin-si (KR); and Hyun Wook Choi, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Jul. 19, 2022, as Appl. No. 17/813,489.
Claims priority of application No. 10-2022-0006039 (KR), filed on Jan. 14, 2022.
Prior Publication US 2023/0230543 A1, Jul. 20, 2023
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel connected to first to fifth scan lines, a first emission control line, and a data line;
a scan driver configured to supply first to fifth scan signals respectively to the first to fifth scan lines;
an emission driver configured to supply a first emission control signal to the first emission control line; and
a data driver configured to supply a data signal to the data line,
wherein the pixel comprises:
a light emitting element;
a first transistor connected between a first node and a second node, the first transistor generating a driving current flowing from a first power line receiving a first power voltage to a second power line receiving a second power voltage through the light emitting element;
a second transistor connected between the data line and the first node, the second transistor being turned on in response to the fourth scan signal;
a third transistor connected between the second node and a third node connected to a gate electrode of the first transistor, the third transistor being turned on in response to the second scan signal;
a fourth transistor connected between the third node and a third power line through which a third power voltage is provided, the fourth transistor being turned on in response to the first scan signal;
a fifth transistor connected between the first node and a fourth node, the fifth transistor being turned on in response to the third scan signal;
a sixth transistor connected between the first node and the first power line, the sixth transistor being turned off in response to the first emission control signal;
a first capacitor connected between the first power line and the fourth node; and
a second capacitor connected between the third node and the fourth node, and
wherein the emission driver sets the scan signals so that a period in which the second transistor is turned on and a period in which the third transistor is turned on do not overlap with each other.