US 11,842,266 B2
Processing-in-memory (PIM) device, controller for controlling the PIM device, and PIM system including the PIM device and the controller
Choung Ki Song, Yongin-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 4, 2021, as Appl. No. 17/140,940.
Application 17/140,940 is a continuation in part of application No. 17/090,462, filed on Nov. 5, 2020, granted, now 11,537,323.
Claims priority of provisional application 62/959,641, filed on Jan. 10, 2020.
Claims priority of provisional application 62/958,223, filed on Jan. 7, 2020.
Claims priority of application No. 10-2020-0006902 (KR), filed on Jan. 17, 2020.
Prior Publication US 2021/0209455 A1, Jul. 8, 2021
Int. Cl. G06N 3/063 (2023.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/523 (2013.01); G06F 7/5443 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A processing-in-memory (PIM) device comprising:
a plurality of multiplication/accumulation (MAC) operators included in each of a plurality of channels, wherein each of the plurality of MAC operators is configured to perform a MAC arithmetic operation using weight data of a weight matrix;
a plurality of memory banks included in each of the plurality of channels and configured to transmit the weight data of the weight matrix to the plurality of MAC operators; and
a plurality of global buffers disposed in the plurality of channels, respectively,
wherein in each of the plurality of channels, each of the plurality of global buffers is configured to transmit vector data of a vector matrix to each of the plurality of MAC operators, and
wherein the weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.