US 11,842,193 B2
Processing-in-memory (PIM) device
Choung Ki Song, Yongin-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 15, 2022, as Appl. No. 17/865,903.
Application 17/865,903 is a continuation of application No. 17/145,245, filed on Jan. 8, 2021, granted, now 11,422,803.
Application 17/145,245 is a continuation in part of application No. 17/090,462, filed on Nov. 5, 2020, granted, now 11,537,323.
Claims priority of provisional application 62/958,609, filed on Jan. 8, 2020.
Claims priority of provisional application 62/958,223, filed on Jan. 7, 2020.
Claims priority of application No. 10-2020-0006902 (KR), filed on Jan. 17, 2020.
Prior Publication US 2022/0350600 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 7/544 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 7/5443 (2013.01); G06F 9/30036 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An arithmetic device comprising:
an arithmetic circuit configured to perform an arithmetic operation of a first data and a second data to output arithmetic result data; and
a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation, and
wherein the data output unit includes:
a data selector configured to receive the bias data and the arithmetic result data and configured to selectively output the bias data or the arithmetic result data based on a selection signal; and
a data output latch configured to receive output data of the data selector to feedback the output data of the data selector to the arithmetic circuit in response to a clock signal transmitted a clock terminal;
a delay circuit configured to receive and delay the selection signal by a certain time to output a delayed selection signal; and
an OR gate configured to perform a logical OR operation of an output signal of the delay circuit and an arithmetic output latch signal to output a result of the logical OR operation to the clock terminal of the data output latch as the clock signal.