US 11,842,168 B2
Circuit architecture for determining threshold ranges and values of a dataset
Sai Lalith Chaitanya Ambatipudi, Hyderabad (IN); Vamsi Krishna Nalluri, Sunnyvale, CA (US); Sandeep Jayant Sathe, Pune Maharashtra (IN); Chaithanya Dudha, San Jose, CA (US); and Krishna Kishore Bhagavatula, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Sep. 25, 2021, as Appl. No. 17/485,382.
Prior Publication US 2023/0096400 A1, Mar. 30, 2023
Int. Cl. G06F 7/50 (2006.01); G06F 7/02 (2006.01); G06F 17/18 (2006.01)
CPC G06F 7/50 (2013.01) [G06F 7/026 (2013.01); G06F 17/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic system, comprising:
a mapping circuit configured to receive a plurality of input samples of a dataset within a defined range of values, wherein the mapping circuit is configured to perform a plurality of comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values;
wherein, for each comparison, the mapping circuit generates an indication signal specifying an indication value, the indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison;
an adder circuit configured to generate, for each comparison value, a sum by summing each indication value corresponding to the comparison value, wherein each indication value is associated with a single comparison value;
a memory configured to maintain a plurality of counts corresponding to the plurality of comparison values, wherein each count of the plurality of counts is updated by a respective sum; and
a threshold detection circuit configured to determine, for the dataset, a threshold value based on the plurality of counts read from the memory;
wherein the plurality of counts form a cumulative distribution function of the plurality of input samples stored in the memory.