US 11,842,135 B2
Integrated circuit layout generation method and system
Ke-Ying Su, Taipei (TW); Ke-Wei Su, Zhubei (TW); Keng-Hua Kuo, Hsinchu (TW); and Lester Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Sep. 24, 2020, as Appl. No. 17/031,610.
Application 17/031,610 is a continuation of application No. 16/294,735, filed on Mar. 6, 2019, granted, now 10,796,059.
Claims priority of provisional application 62/646,808, filed on Mar. 22, 2018.
Prior Publication US 2021/0019467 A1, Jan. 21, 2021
Int. Cl. G06F 30/392 (2020.01); G06F 30/20 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/20 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of generating an integrated circuit (IC) layout diagram of an IC device, the method comprising:
receiving the IC layout diagram of the IC device, the IC layout diagram comprising a gate region having a width across an active region;
dividing the width into a plurality of width segments based on a location of a gate via; and
performing a simulation based on the IC layout diagram including an effective resistance calculated using at least one width segment of the plurality of width segments.