US 11,842,132 B1
Multi-cycle power analysis of integrated circuit designs
George Guangqiu Chen, Cupertino, CA (US); and Solaiman Rahim, San Francisco, CA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,992.
Int. Cl. G06F 30/30 (2020.01); G06F 30/3315 (2020.01); G06F 119/12 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/3315 (2020.01) [G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 12 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a plurality of value changes corresponding to timestamped logic value changes in a plurality of recorded signals from a verification run of an integrated circuit design;
generating a plurality of recorded logic vectors from the plurality of value changes, each of the plurality of recorded logic vectors being associated with a corresponding signal identifier, each of the plurality of recorded logic vectors comprising a plurality of recorded logic values over a window of consecutive clock cycles computed from one or more logic value changes of one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles;
determining, by a processor, a plurality of inferred logic vectors comprising a plurality of inferred logic values corresponding to signals output by a plurality of cells of the integrated circuit design based on propagating the plurality of recorded logic values of the plurality of recorded logic vectors through the plurality of cells; and
computing per-cycle power characteristics of the integrated circuit design based on the plurality of recorded logic vectors and the plurality of inferred logic vectors.