US 11,842,079 B2
Memory controller and memory control method that decides an order of issuing dram commands based on whether a command has a penalty period
Motohisa Ito, Chiba (JP); and Daisuke Shiraishi, Tokyo (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Apr. 4, 2022, as Appl. No. 17/712,590.
Application 17/712,590 is a continuation of application No. 17/004,240, filed on Aug. 27, 2020, granted, now 11,435,951.
Claims priority of application No. 2019-158934 (JP), filed on Aug. 30, 2019.
Prior Publication US 2022/0229602 A1, Jul. 21, 2022
Int. Cl. G06F 3/06 (2006.01); G11C 11/406 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0629 (2013.01); G06F 3/0653 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G11C 11/40622 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory controller that is configured to be able to issue a command for a DRAM, comprising:
a storage unit configured to store one or more requests to the DRAM;
a deciding unit configured to decide an issuance order of the one or more requests stored in the storage unit; and
an issuance unit configured to issue a DRAM command based on the issuance order decided by the deciding unit,
wherein in a period from the issuance of a preceding DRAM command targeting a first bank until a command targeting the first bank and having a penalty period is issued, if another DRAM command targeting a second bank different from the first bank can be issued, the deciding unit decides the issuance order so that the other DRAM command that can be issued is to be issued before the command targeting the first bank and having the penalty period.