US 11,842,078 B2
Asynchronous interrupt event handling in multi-plane memory devices
Andrea Giovanni Xotta, Avezzano (IT); Guido Luciano Rizzo, Avezzano (IT); Umberto Siciliani, Rubano (IT); Tommaso Vali, Avezzano (IT); Luca De Santis, Avezzano (IT); and Walter Di Francesco, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 31, 2022, as Appl. No. 17/589,080.
Claims priority of provisional application 63/202,655, filed on Jun. 18, 2021.
Prior Publication US 2022/0405013 A1, Dec. 22, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 9/48 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 9/4812 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array configured with a plurality of memory planes; and
control logic, operatively coupled with the memory array, to perform operations comprising:
performing a plurality of asynchronous memory access operations on the plurality of memory planes;
detecting an occurrence of an asynchronous interrupt event;
initiating a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times; and
in response to a first memory access operation of the plurality of asynchronous memory access operations ending:
asserting a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes; and
asserting a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.