US 11,842,048 B2
Process acceleration for software defined storage
Lionel Corbet, Milpitas, CA (US); Phillip Edward Straw, Newark, CA (US); Steve Hardwick, Austin, TX (US); and Harry Richardson, Lamarsh (GB)
Assigned to SOFTIRON LIMITED, London (GB)
Filed by SOFTIRON LIMITED, Chilworth (GB)
Filed on Oct. 20, 2021, as Appl. No. 17/505,890.
Claims priority of provisional application 63/094,618, filed on Oct. 21, 2020.
Prior Publication US 2022/0121373 A1, Apr. 21, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor;
a memory communicatively coupled to the processor;
an acceleration framework circuit communicatively coupled to the memory and the processor; and
a device driver configured to:
receive a request for data manipulation by a software defined storage (SDS) application;
determine whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit;
based upon the determination of whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit, selectively cause the request to be executed by the acceleration framework circuit or the SDS application through execution on the processor;
determine a likely next task; and
preconfigure the acceleration framework circuit to execute an SDS operation to execute the likely next task.