US 11,841,982 B2
Partitioning circuits for execution of sequential secure computation code on multiple processors
Hayim Shaul, Kfar Saba (IL); Ehud Aharoni, Kfar Saba (IL); Dov Murik, Haifa (IL); Omri Soceanu, Haifa (IL); Gilad Ezov, Nesher (IL); Lev Greenberg, Haifa (IL); and Evgeny Shindin, Nesher (IL)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 20, 2021, as Appl. No. 17/505,964.
Prior Publication US 2023/0119283 A1, Apr. 20, 2023
Int. Cl. G06F 21/72 (2013.01); H04L 9/00 (2022.01); G06F 21/60 (2013.01); G06F 21/14 (2013.01)
CPC G06F 21/72 (2013.01) [G06F 21/602 (2013.01); H04L 9/008 (2013.01); G06F 21/14 (2013.01); H04L 2209/125 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system, comprising a processor to:
receive sequential secure computation code;
execute the sequential secure computation code using a replaced library that logs an operation type and inputs for each of a plurality of logged operations;
generate a circuit based on the logged operations performed in response to execution of the sequential secure computation code;
modify the circuit based on a cost function;
partition the modified circuit into a plurality of sub-circuits such that data to be sent between the sub-circuits is reduced; and
assign the plurality of the sub-circuits to different processors for execution.