US 11,841,926 B2
Image fusion processor circuit for dual-mode image fusion architecture
Maxim Smirnov, Portland, OR (US); and Kaiming Liu, Santa Clara, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 10, 2021, as Appl. No. 17/173,074.
Prior Publication US 2022/0253651 A1, Aug. 11, 2022
Int. Cl. G06T 3/00 (2006.01); G06T 3/40 (2006.01); G06V 10/75 (2022.01); G06F 18/25 (2023.01)
CPC G06F 18/251 (2023.01) [G06T 3/0093 (2013.01); G06T 3/40 (2013.01); G06V 10/751 (2022.01)] 20 Claims
OG exemplary drawing
 
1. An image fusion processor, comprising:
a first image fusion circuit configured to:
blend high frequency components of an unscaled layer of each of a first raw image pyramid and a second raw image pyramid to generate a fused high frequency component for the unscaled layer, and
aggregate the fused high frequency component for the unscaled layer with a fused image for a first downscaled layer to generate a fused raw image corresponding to an unscaled layer of a fused raw image pyramid; and
a second image fusion circuit coupled to the first image fusion circuit, the second image fusion circuit configured to:
generate the fused image for the first downscaled layer by blending high frequency components of the first downscaled layer of each of the first and second raw image pyramids to generate a high frequency component of the fused image, and
aggregate the generated high frequency component with a fused image corresponding to a subsequent downscaled layer of the first and second raw image pyramids.