CPC G06F 13/4282 (2013.01) [G06F 9/466 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01)] | 20 Claims |
1. A Peripheral Component Interconnect Express (PCIe) device, comprising:
at least one Direct Memory Access (DMA) device configured to execute a first function and a second function;
a first buffer configured to store a plurality of first transaction layer packets received from the first function and the second function;
a second buffer configured to store a plurality of second transaction layer packets including first source transaction layer packets from the first function and second source transaction layer packets from the second function; and
a buffer controller configured to, when a first buffer of a switch is full, change features of the plurality of second transaction layer packets to realign an order in which the plurality of second transaction layer packets are to be output from the second buffer to a second buffer of the switch, based on IDs of the plurality of second transaction layer packets.
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