US 11,841,805 B2
Memory system for storing map data in host memory and operating method of the same
Eu Joon Byun, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 29, 2022, as Appl. No. 17/877,135.
Application 17/877,135 is a continuation of application No. 16/455,961, filed on Jun. 28, 2019, granted, now 11,429,538.
Claims priority of application No. 10-2018-0144914 (KR), filed on Nov. 21, 2018.
Prior Publication US 2022/0365884 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/123 (2016.01); G06F 9/30 (2018.01); G06F 12/1027 (2016.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01)
CPC G06F 12/123 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0652 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 9/30043 (2013.01); G06F 12/0246 (2013.01); G06F 12/1027 (2013.01); G06F 3/0679 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A memory controller for controlling a memory device, the memory controller comprising:
a buffer memory configured to store map data including mapping information of logical addresses of data provided from an external host and physical addresses of memory cells included in the memory device, wherein the physical addresses correspond to the logical addresses, respectively;
a host control circuit configured to provide host map data which includes some of the map data to the external host;
a map data control block configured to:
receive a read request from the external host, and
check a history of the map data transmitted to the external host in order to determine from the history that same map data is stored in both the external host and the buffer memory, wherein the same map data includes target mapping information corresponding to a logical address of the read request; and
a flash control circuit configured to acquire the target mapping information and process the read request according to the target mapping information.