US 11,841,803 B2
GPU chiplets using high bandwidth crosslinks
Skyler J. Saleh, San Diego, CA (US); Samuel Naffziger, Fort Collins, CO (US); Milind S. Bhagavat, Santa Clara, CA (US); and Rahul Agarwal, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jun. 28, 2019, as Appl. No. 16/456,287.
Prior Publication US 2020/0409859 A1, Dec. 31, 2020
Int. Cl. G06F 12/08 (2016.01); G06F 12/0897 (2016.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/0897 (2013.01) [G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a central processing unit (CPU) communicably coupled to a first graphics processing unit (GPU) chiplet of a GPU chiplet array, wherein the GPU chiplet array includes:
the first GPU chiplet communicably coupled to the CPU via a bus; and
a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink, wherein the passive crosslink is dedicated for inter-chiplet communications.