US 11,841,796 B2
Scratchpad memory in a cache
Chinnakrishnan Ballapuram, San Jose, CA (US); Saira Samar Malik, Lafayette, IN (US); and Taeksang Song, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 5, 2022, as Appl. No. 17/569,336.
Claims priority of provisional application 63/140,094, filed on Jan. 21, 2021.
Prior Publication US 2022/0229778 A1, Jul. 21, 2022
Int. Cl. G06F 12/0802 (2016.01); G06F 12/0888 (2016.01); G06F 12/0868 (2016.01); G06F 12/02 (2006.01); G11C 5/10 (2006.01); G11C 5/02 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method performed by a memory device, comprising:
operating a portion of a volatile memory in a cache mode having non-deterministic latency for satisfying requests from a host device, the cache mode associated with data movement between the portion and a non-volatile memory;
monitoring an output pin of a register in the memory device, the output pin associated with the portion and indicative of an operating mode of the portion;
determining, based at least in part on monitoring the output pin of the register and on a latency demand, an expected access frequency, or both, of a set of data to be stored at the portion of the volatile memory, whether to change the operating mode of the portion from the cache mode to a scratchpad mode having deterministic latency for satisfying requests from the host device, the scratchpad mode for operating the portion independent of the non-volatile memory; and
operating the portion of the volatile memory in the scratchpad mode based at least in part on the determining to change the operating mode of the portion.