CPC G06F 11/1044 (2013.01) [G11C 29/04 (2013.01); G06F 11/277 (2013.01)] | 20 Claims |
1. A semiconductor memory device comprising:
a buffer die configured to communicate with an external device; and
a plurality of memory dies stacked on the buffer die and configured to connect to the buffer die through a plurality of through silicon vias (TSVs),
wherein each of the plurality of memory dies includes:
a memory cell array which includes a plurality of memory cell rows, each including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
an error correction code (ECC) engine, in a normal mode, configured to perform Reed-Solomon (RS) encoding on data stored in the memory cell array and configured to perform a RS decoding on data read from the memory cell array to correct an error of the read data by unit of a symbol; and
a test circuit, in a test mode, configured to:
generate a test syndrome and an expected decoding status flag indicating error status of the test syndrome;
receive a test parity data and a decoding status flag, the test parity data generated by the ECC engine based on the test syndrome, the decoding status flag indicating error status of the test parity data; and
determine whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.
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