US 11,841,396 B1
United states test controller for system-on-chip validation
Sameer Vaidya, Campbell, CA (US); Supaket Katchmart, San Jose, CA (US); Vivek Khanzode, Sunnyvale, CA (US); Pallavi Joshi, Milpitas, CA (US); Henri Sutioso, Saratoga, CA (US); Naim Siemsen-Schumann, Fremont, CA (US); and Hongying Sheng, San Jose, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Mar. 21, 2022, as Appl. No. 17/655,706.
Claims priority of provisional application 63/304,355, filed on Jan. 28, 2022.
Claims priority of provisional application 63/164,333, filed on Mar. 22, 2021.
Int. Cl. G01R 31/317 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/31701 (2013.01) [G01R 31/3177 (2013.01); G01R 31/31724 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method for testing a read data channel of a storage device controller, where the storage device controller includes drive controller circuitry configured to control writing or fetching of data to or from, respectively, a storage medium, read data channel circuitry for interfacing between the drive controller circuitry and the storage medium, and test controller circuitry separate from the drive controller circuitry and configured to test the read data channel circuitry by issuing test commands simulating the writing or fetching of data to or from, respectively, the storage medium, the method comprising:
coupling a source of test data signals to the read data channel; and
coupling the read data channel circuitry to the test controller circuitry instead of to the separate drive controller circuitry to test execution by the read data channel of the test commands on the test data signals.