US 12,495,722 B2
Suppression of void-formation of PCM materials
Cheng-Wei Cheng, White Plains, NY (US); Robert L. Bruce, White Plains, NY (US); Matthew Joseph BrightSky, Armonk, NY (US); and Gloria Wing Yun Fraczak, Queens, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 6, 2021, as Appl. No. 17/457,750.
Prior Publication US 2023/0180636 A1, Jun. 8, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/023 (2023.02) [H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/068 (2023.02); H10N 70/231 (2023.02); H10N 70/841 (2023.02); H10N 70/883 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor structure, the semiconductor structure comprising:
a bottom electrode directly on top of a substrate;
a patterned dielectric layer on top of the bottom electrode, wherein the patterned dielectric layer includes one or more structures;
a liner layer on either sidewall of each structure of the one or more structures and directly on top of a portion of the bottom electrode;
a selectivity promotion layer on either each liner layer on either sidewall of each structure of the one or more structures; and
a phase change memory material layer within the one or more structures between the selectivity promotion layer on either sidewall of each structure of the one or more structures and, in a trapezoidal shape, directly on top of a frontside surface of the liner layer, a frontside surface of the selectivity promotion layer, and a portion of a frontside surface of the patterned dielectric layer.