US 12,495,638 B2
Process for manufacturing a low-noise photodetector device in a CdHgTe substrate
François Boulard, Grenoble (FR); Jean-Paul Chamonal, Grenoble (FR); Clément Lobre, Grenoble (FR); and Florent Rochette, Grenoble (FR)
Assigned to COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, Paris (FR)
Appl. No. 17/995,605
Filed by COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, Paris (FR)
PCT Filed Apr. 2, 2021, PCT No. PCT/FR2021/050587
§ 371(c)(1), (2) Date Oct. 6, 2022,
PCT Pub. No. WO2021/205102, PCT Pub. Date Oct. 14, 2021.
Claims priority of application No. 2003595 (FR), filed on Apr. 9, 2020; and application No. 2008678 (FR), filed on Aug. 25, 2020.
Prior Publication US 2023/0155043 A1, May 18, 2023
Int. Cl. H10F 77/123 (2025.01); H10F 30/222 (2025.01); H10F 71/00 (2025.01); H10F 77/00 (2025.01); H10F 77/14 (2025.01)
CPC H10F 77/1237 (2025.01) [H10F 30/222 (2025.01); H10F 71/1253 (2025.01); H10F 77/14 (2025.01); H10F 77/933 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method for manufacturing a photodetection device, which includes the following steps:
a) depositing, over a semiconductor substrate of CdxHg1-xTe, a source coating which includes, at least, one cadmium-rich layer having a higher average concentration of cadmium than the semiconductor substrate, with the cadmium-rich layer in direct physical contact with an upper face of the semiconductor substrate;
b) making a first etching mask, superimposed on the source coating on the side opposite to the semiconductor substrate;
c) a first etching step, to etch the source coating throughout the first etching mask and to thus form at least one first through opening in the source coating, the source coating fitted with the at least one first through opening being called structured coating;
d) a second etching step, to enlarge at least one second through opening in a structure on top of the structured coating on completion of the first etching step, and to thus form a second etching mask;
e) injecting acceptor doping elements into the semiconductor substrate, throughout through openings of the second etching mask, with the acceptor doping elements that locally pass through the structured coating;
f) activating and diffusing the acceptor doping elements, to form at least one P doped region in the semiconductor substrate;
g) selective interdiffusion annealing of cadmium, implemented after step f) or at least partially simultaneously with step f), during which the cadmium atoms diffuse from the structured coating towards the at least one P doped region, so as to form in each P doped region a concentrated well with at least one intermediate gap area and at least one high gap area, where the intermediate gap area has an average concentration of cadmium strictly lower than the average concentration of cadmium in the high gap area; and
h) depositing a metal layer coming into contact with the semiconductor substrate at the at least one first through opening in the structured coating, to form at least one electrical contact pad.