	US 12,495,592 B2
	Semiconductor substrate, semiconductor device, and manufacturing methods of the same
Takuji Maekawa, Kyoto (JP); and Mitsuru Morimoto, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jun. 5, 2024, as Appl. No. 18/734,613.
Application 18/734,613 is a continuation of application No. 17/588,558, filed on Jan. 31, 2022, granted, now 12,074,201.
Application 17/588,558 is a continuation of application No. PCT/JP2020/029516, filed on Jul. 31, 2020.
Claims priority of application No. 2019-142403 (JP), filed on Aug. 1, 2019; application No. 2019-142405 (JP), filed on Aug. 1, 2019; application No. 2019-142409 (JP), filed on Aug. 1, 2019; and application No. 2019-142410 (JP), filed on Aug. 1, 2019.
Prior Publication US 2024/0321970 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 62/832 (2025.01); H01L 21/02 (2006.01); H10D 8/60 (2025.01); H10D 12/00 (2025.01); H10D 30/66 (2025.01); H10D 62/40 (2025.01)

CPC H10D 62/8325 (2025.01) [H01L 21/02378 (2013.01); H01L 21/02433 (2013.01); H01L 21/02516 (2013.01); H01L 21/02529 (2013.01); H01L 21/02595 (2013.01); H10D 62/405 (2025.01); H10D 8/60 (2025.01); H10D 12/441 (2025.01); H10D 30/66 (2025.01); H10D 30/668 (2025.01)]

26 Claims

1. A semiconductor substrate comprising:

a first layer that is formed of a single crystal SiC semiconductor; and

a second layer that is formed on a surface of the first layer and is formed of a SiC semiconductor which includes a polycrystalline structure, wherein

the second layer also includes a single crystal SiC semiconductor, a portion of the second layer that is formed from the first layer to a predetermined height is formed of a single crystal SiC semiconductor, and a remainder of the second layer that is a portion formed beyond the predetermined height from the first layer is formed of a polycrystal SiC semiconductor, and

an interface is not observed on the junction surface between the first layer and the second layer by TEM observation.