| CPC H10D 30/62 (2025.01) [H10D 30/0243 (2025.01); H10D 30/0245 (2025.01); H10D 30/6219 (2025.01); H10D 62/118 (2025.01); H10D 62/83 (2025.01); H10D 64/017 (2025.01); H10D 84/834 (2025.01)] | 20 Claims |
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1. A memory cell comprising:
a substrate;
at least two pull-up transistors, wherein a first pull-up transistor of the at least two pull-up transistors is a finFET transistor that includes:
a semiconductor material extending above the substrate in a first horizontal direction along the substrate and extending vertically continuously to a first height above the substrate; and
a gate electrode extending in a second horizontal direction perpendicular to the first horizontal direction over a top and sidewalls of the semiconductor material;
at least two pull-down transistors, wherein a first pull-down transistor of the at least two pull-down transistors is a nanosheet FET transistor (NFET) that includes:
a stacked semiconductor channel region extending in the first horizontal direction, individual semiconductor channel regions of the stacked semiconductor channel region being stacked vertically above the substrate and being separated by respective portions of the gate electrode;
a source/drain region adjacent the stacked semiconductor channel region, the source/drain region extending from the substrate and including dopants of a first conductivity type;
an anti-punch-through region in the substrate and underlying the stacked semiconductor channel region and the source/drain region, the anti-punch-through region including dopants of a second conductivity type, the second conductivity type being opposite the first conductivity type; and
at least two pass-gate transistors, wherein a first pass-gate transistor of the at least two pass-gate transistors is an NFET that includes:
a second stacked semiconductor channel region extending in the first horizontal direction, individual semiconductor channel regions of the second stacked semiconductor channel region being stacked vertically above the substrate and being separated by respective portions of a second gate electrode, wherein the anti-punch-through region extends under the second stacked semiconductor channel region.
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