| CPC H10D 30/015 (2025.01) [H10D 30/475 (2025.01); H10D 64/111 (2025.01); H10D 64/251 (2025.01); H10D 62/8503 (2025.01)] | 11 Claims |
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1. A power semiconductor device comprising:
a substrate;
a channel layer on the substrate;
a barrier layer on the channel layer, wherein the barrier layer comprises a plurality of isolation regions spaced apart from each other in a plan view, and each of the plurality of isolation regions comprises an insulation material;
a capping layer having a first conductivity type on the barrier layer;
a gate electrode on the capping layer;
a source electrode and a drain electrode on the barrier layer, spaced apart from the gate electrode;
an insulation film on the barrier layer, and
a field plate on the insulation film, the field plate being electrically connected to the drain electrode,
wherein the barrier layer is discontinuous from the source electrode to the drain electrode.
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