| CPC H04L 1/18 (2013.01) | 12 Claims |

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1. An apparatus, comprising:
at least one processor; and
at least one memory including computer code;
the at least one memory and the computer code configured to, with the at least one processor, cause the apparatus at least to:
receive at least a first subset of a plurality of data packets of a data burst over a first transmission leg;
determine a burst reception indication for the data burst based on at least the first subset of the plurality of data packets and a reception status of at least a second subset of the plurality of data packets associated with a second transmission leg, wherein a transmission order of the plurality of data packets is different for the first transmission leg and the second transmission leg, and wherein the burst reception indication is indicative of acknowledgment and/or non-acknowledgement of at least one of the plurality of data packets; and
cause transmission of the burst reception indication on the first transmission leg and/or the second transmission leg; and
wherein the at least one memory and the computer code are further configured to, with the at least one processor, cause the apparatus to:
receive the first subset of data packets at a first instance of a lower layer of a protocol stack;
receive the reception status of at least the second subset of the plurality of data packets from a second instance of the lower layer of the protocol stack; and
transmit the burst reception indication at the lower layer of the protocol stack.
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