US 12,494,800 B2
Apparatus and method for constant detection during compress operations
James David Guilford, Northborough, MA (US); Vinodh Gopal, Westborough, MA (US); Daniel Frederick Cutter, Maynard, MA (US); and Kirk Yap, Westborough, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,989.
Prior Publication US 2023/0198548 A1, Jun. 22, 2023
Int. Cl. H03M 7/30 (2006.01); G06F 3/06 (2006.01)
CPC H03M 7/3084 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0641 (2013.01); G06F 3/0679 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
compression circuitry to perform compression operations on a memory block;
constant detection circuitry to, concurrently with performance of the compression operations on the memory block, perform constant check operations that comprise a determination of whether the memory block is a constant data block comprised of only repeat instances of a constant value; and
controller circuitry to associate a first indication with the memory block based on the determination that the memory block is a constant data block, wherein the first indication is usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.