US 12,494,780 B2
Interface circuit, control method thereof, chip, and terminal device
Zhaohua Qian, Shanghai (CN); Jingjing Wang, Shenzhen (CN); Yanqin Chen, Shanghai (CN); and Jiandong Ke, Shanghai (CN)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Sep. 15, 2023, as Appl. No. 18/468,475.
Application 18/468,475 is a continuation of application No. PCT/CN2021/081342, filed on Mar. 17, 2021.
Prior Publication US 2024/0007106 A1, Jan. 4, 2024
Int. Cl. H03K 17/687 (2006.01); G06F 3/14 (2006.01)
CPC H03K 17/6872 (2013.01) [G06F 3/14 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An interface circuit, comprising:
a first positive-channel metal oxide semiconductor (PMOS) transistor;
an input signal control circuit, comprising a first input end, a second input end, and an output end;
a bias circuit, comprising a first end, a second end, a third end, a substrate bias voltage generation end, and a bias voltage generation end;
a signal input end; and
an input/output end;
wherein the first input end of the input signal control circuit is connected to the signal input end, the second input end of the input signal control circuit is connected to the bias voltage generation end, and the output end of the input signal control circuit is connected to a gate of the first PMOS transistor;
wherein a first electrode of the first PMOS transistor is connected to a high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input/output end;
wherein the substrate bias voltage generation end is connected to a substrate of the first PMOS transistor, the first end of the bias circuit is coupled to the high-level power supply end, the second end of the bias circuit is coupled to the input/output end, and the third end of the bias circuit is coupled to a ground end;
wherein the input signal control circuit is configured to transmit an electrical signal of the signal input end or an electrical signal of the bias voltage generation end bias to the gate of the first PMOS transistor; and
wherein the bias circuit is configured to perform connection and conduction between the high-level power supply end and the substrate bias voltage generation end, or perform connection and conduction between the input/output end and the substrate bias voltage generation end.