US 12,494,469 B1
Low cost solution for 2.5D and 3D packaging using USR chiplets
Mohsen F. Rad, Las Vegas, NV (US)
Assigned to Eliyan Corp., Santa Clara, CA (US)
Filed by Eliyan Corporation, Santa Clara, CA (US)
Filed on May 23, 2023, as Appl. No. 18/200,891.
Application 18/200,891 is a continuation of application No. 16/812,234, filed on Mar. 6, 2020, granted, now 11,855,056.
Claims priority of provisional application 62/941,461, filed on Nov. 27, 2019.
Claims priority of provisional application 62/818,752, filed on Mar. 15, 2019.
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/5384 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 24/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chiplet-based system-in-packages (SiP), comprising:
a non-silicon substrate;
a memory device coupled to the non-silicon substrate and comprising
a first integrated circuit (IC) chip assembly comprising
a first secondary substrate comprising first mold material of a mold material type;
a first IC memory chip coupled to the first mold material in accordance with a wafer-level fan out (WLFO) process;
a second IC chip assembly stacked with the first IC chip assembly, the second IC chip assembly comprising
a second secondary substrate comprising second mold material of the mold material type;
a second IC memory chip coupled to the second mold material in accordance with the wafer-level fan out (WLFO) process;
through-mold vias coupling the first IC chip assembly to the second IC chip assembly; and
a processor chip assembly coupled to the non-silicon substrate and coupled to the memory device.