US 12,494,465 B2
Display device and tile-shaped display device including the same
Byeong Kyun Choi, Suwon-si (KR); Byoung Yong Kim, Seoul (KR); and Jae Phil Lee, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Jan. 23, 2023, as Appl. No. 18/158,401.
Claims priority of application No. 10-2022-0012359 (KR), filed on Jan. 27, 2022; and application No. 10-2022-0051145 (KR), filed on Apr. 26, 2022.
Prior Publication US 2023/0238398 A1, Jul. 27, 2023
Int. Cl. H01L 25/16 (2023.01); G09G 3/3233 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H01L 23/00 (2006.01)
CPC H01L 25/167 (2013.01) [G09G 3/3233 (2013.01); H10D 86/443 (2025.01); H10D 86/60 (2025.01); G09G 2300/026 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2330/04 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05138 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/0518 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05561 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2924/0106 (2013.01); H01L 2924/0549 (2013.01); H01L 2924/12041 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate including a display area in which a plurality of sub-pixels is arranged, and a non-display area at a periphery of the display area;
a transistor array layer on a first surface of the substrate; and
a plurality of light emitting elements in the display area on the transistor array layer, and corresponding to the plurality of sub-pixels,
wherein the transistor array layer comprises:
a plurality of pixel drivers in a circuit area of the display area, each of the plurality of pixel drivers corresponding to the plurality of sub-pixels, and each of the plurality of pixel drivers comprising at least one transistor;
two or more gate drivers in the circuit area, spaced from each other in one direction, and configured to supply each signal to gate lines connected to the plurality of pixel drivers;
a first gate voltage supply line around the circuit area of the display area, and extending in the one direction; and
two or more first gate voltage auxiliary lines extending in the other direction crossing the one direction, and connected between the first gate voltage supply line and each of the two or more gate drivers, and
one end of each of the two or more first gate voltage auxiliary lines is connected to the first gate voltage supply line through at least one first gate voltage line contact hole, and is further spaced from an edge of the substrate adjacent to the first gate voltage supply line than the first gate voltage supply line.