US 12,494,429 B2
Power planning method, chip device, and non-transitory computer readable medium
Cheng-Chen Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/223,069.
Claims priority of application No. 112101289 (TW), filed on Jan. 12, 2023.
Prior Publication US 2024/0243063 A1, Jul. 18, 2024
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 23/5226 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A power planning method, capable of being implemented by a circuit that includes a first circuit layer and a second circuit layer, wherein the second circuit layer is disposed on one side of the first circuit layer, the first circuit layer includes a plurality of power rails and at least one first standard circuit unit, and the second circuit layer includes the plurality of power rails, wherein the power planning method comprises:
calculating an unused routing area and a used routing area of each of the first circuit layer and the second circuit layer of the circuit, wherein the used routing area of each of the first circuit layer and the second circuit layer has at least the plurality of power rails disposed thereon, and the unused routing area of each of the first circuit layer and the second circuit layer has none of the plurality of power rails disposed thereon; and
disposing a plurality of auxiliary power stripes or a plurality of auxiliary via pillars to connect the plurality of power rails of the first circuit layer and the plurality of power rails of the second circuit layer.