| CPC G11C 29/10 (2013.01) [G11C 29/12 (2013.01); G11C 5/04 (2013.01)] | 20 Claims |
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1. A memory subsystem operable in a computer system, the computer system including a memory controller configurable to communicate with the memory subsystem via a set of system signal lines including system control/address (C/A) signal lines and system data signal lines, the memory subsystem comprising:
memory devices having C/A ports and data ports and configurable to receive input C/A signals via the C/A ports and to receive/output data signals via the data ports in response to the input C/A signals;
a control module coupled to the C/A ports of the memory devices via subsystem C/A signal lines; and
a data module coupled to the data ports of the memory devices via subsystem data signal lines;
wherein the memory subsystem is operable in a normal mode and a test mode;
wherein, during the normal mode:
the control module is configured to receive system C/A signals from the memory controller via the system C/A signal lines, and to transmit subsystem C/A signals to at least some of the memory devices based on the system C/A signals; and
the data module is configured to propagate data signals between the subsystem data signal lines and the system data signal lines, the data signals being received or output by at least some of the memory devices in response to the subsystem C/A signals;
wherein, during the test mode:
the control module is configured to transmit test C/A signals to at least some of the memory devices;
the data module is configured to isolate data paths from the system data signal lines to the subsystem data signal lines; and
the data module is further configured to generate test data signals and to transmit the test data signals to at least some of the memory devices via at least some of the subsystem data signal lines, the test signals being received by and written into memory locations in at least some of the memory devices in response to the test C/A signals.
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