US 12,494,251 B2
Memory circuitry and method used in forming memory circuitry
Jiewei Chen, Meridian, ID (US); Jordan D. Greenlee, Boise, ID (US); Shuangqiang Luo, Boise, ID (US); and Silvia Borsari, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 26, 2022, as Appl. No. 17/896,775.
Prior Publication US 2024/0071495 A1, Feb. 29, 2024
Int. Cl. H01L 23/522 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction, insulative material being atop treads of the stairs, individual of the treads comprising conducting material of one of the first conductive tiers in the finished-circuitry construction;
forming conductive-via openings through the insulative material, individual of the conductive-via openings being directly above a corresponding of the individual of the treads;
forming a lining over sidewalls and along a bottom of the individual conductive-via openings to less-than-fill the individual conductive-via openings, the lining comprising at least one of (a): a silicon oxide having dopant therein at a total atomic concentration of 0.1 to 30 percent, the dopant being at least one of carbon, boron and nitrogen; and (b): a silicon nitride having dopant therein at a total atomic concentration of 0.1 to 30 percent, the dopant being at least one of carbon and boron;
treating the lining along the bottom to remove more of the dopant therefrom than removal of the dopant, if any, from the lining that is over the sidewalls;
etching through the lining that is in the bottom selectively relative to the lining that is over the sidewalls to leave the lining over the sidewalls, and exposing the conducting material of the individual treads; and
forming conductive vias in the individual conductive-via openings, the conductive vias being radially-inward relative to the lining that is over the sidewalls and being individually directly electrically coupled to the conducting material of the respective individual tread.