US 12,494,236 B2
Memory device and system device including the same
Yunseok Yang, Suwon-si (KR); Eungchang Lee, Suwon-si (KR); Seula Ryu, Suwon-si (KR); Minhwan An, Suwon-si (KR); Yunkyeong Jeong, Suwon-si (KR); and Chul-Hwan Choo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 19, 2023, as Appl. No. 18/354,869.
Claims priority of application No. 10-2022-0159271 (KR), filed on Nov. 24, 2022.
Prior Publication US 2024/0177749 A1, May 30, 2024
Int. Cl. G11C 8/12 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 5/06 (2013.01); G11C 7/1057 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a base die including a data signal bump configured to receive a data signal, the base die configured to receive a stack selection signal;
a first memory stack including first memory dies sequentially stacked on the base die; and
a second memory stack including second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die,
wherein the base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on the stack selection signal.