US 12,493,783 B2
Data processing array
Rikki J. Crill, Longmont, CO (US); Jonathan C. Baiardo, Carbondale, CO (US); and David A. Bruce, Niwot, CO (US)
Assigned to Look Dynamics, Inc., Longmont, CO (US)
Filed by Look Dynamics, Inc., Longmont, CO (US)
Filed on Jul. 15, 2022, as Appl. No. 17/865,792.
Application 17/865,792 is a continuation of application No. 16/137,522, filed on Sep. 20, 2018, granted, now 11,410,028.
Claims priority of provisional application 62/663,465, filed on Apr. 27, 2018.
Claims priority of provisional application 62/625,711, filed on Feb. 2, 2018.
Claims priority of provisional application 62/561,061, filed on Sep. 20, 2017.
Prior Publication US 2023/0048377 A1, Feb. 16, 2023
Int. Cl. G06N 3/067 (2006.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01)
CPC G06N 3/0675 (2013.01) [G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A data processing array, comprising:
an array of modules arranged in a plurality of rows and a plurality of columns, each module in the array comprising a read and write memory;
a pooling chain comprising a first pooling border line extending along a first side of each module in each column in the array and a second pooling border line extending along a second side of each module in the array, wherein the first border line that extends along the first side of each module intersects and connects with the second border line that extends along the second side of that module to form a border pooling circuit for that module; and wherein the border pooling circuit of each module is connected by a first openable and closeable switch to an adjacent pooling circuit of an adjacent module in the same column and by a second openable and closeable switch to an adjacent pooling circuit of an adjacent module in the same row;
a memory pooling interface in each module connecting the memory in that module to the border pooling circuit of that module for enabling reading data from the memory of that module to the pooling circuit and for enabling writing data from the border pooling circuit to the memory.