US 12,493,730 B2
Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit
Jinwook Jung, Somers, NY (US); Gi-Joon Nam, Chappaqua, NY (US); Jennifer Kazda, Englewood, NJ (US); Gustavo Enrique Tellez, Hyde Park, NY (US); Chau-Chin Huang, Tainan (TW); and Yao-Wen Chang, Taipei (TW)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 2, 2022, as Appl. No. 17/805,198.
Prior Publication US 2023/0394211 A1, Dec. 7, 2023
Int. Cl. G06F 30/3315 (2020.01); G06F 30/327 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/3315 (2020.01) [G06F 30/327 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01)] 15 Claims
OG exemplary drawing
 
1. A method for providing enhanced fabrication and design of an integrated circuit in a computing environment by one or more processors comprising:
clustering one or more latches by augmenting an integer linear program (“ILP”) operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware;
placing the one or more latches based on clustering the one or more latches; and
determining a number of one or more initial candidate local clock buffers by the FLA operation for power and congestion optimization.