| CPC G06F 21/567 (2013.01) [G06F 2221/034 (2013.01)] | 20 Claims |
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1. A scan chain circuit, used for testing a logic circuit, wherein the scan chain circuit comprises:
a plurality of scan chain units, each including:
a plurality of scan flip-flop (SFF), for receiving a plurality of input bit values, wherein after the input bit values are operated by the logic circuit, a plurality of actual operation result bit values are obtained; and
a comparison circuit, for receiving the actual operation result bit values and a plurality of predetermined operation result bit values, wherein each of the predetermined operation result bit values is each of a plurality of predetermined operation results after each of the input bit values is operated by the logic circuit, the comparison circuit compares the actual operation result bit values and the predetermined operation result bit values, and then outputs a bits comparison result bit value.
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