US 12,493,555 B2
Memory controller controlling read operations for prefetching data and storage device including the same
Hyun Jin Chung, Gyeonggi-do (KR); Hee Cheol Kim, Gyeonggi-do (KR); and Byoung Min Jin, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 11, 2023, as Appl. No. 18/535,050.
Claims priority of application No. 10-2023-0087770 (KR), filed on Jul. 6, 2023.
Prior Publication US 2025/0013573 A1, Jan. 9, 2025
Int. Cl. G06F 12/0862 (2016.01); G06F 12/02 (2006.01)
CPC G06F 12/0862 (2013.01) [G06F 12/023 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a read command generator configured to generate read commands instructing a memory device to read, in advance, data to be read-requested from a host;
a cache memory configured to store data read from the memory device according to the read commands;
a read operation controller configured to receive, from the cache memory, data corresponding to a read request of the host in response to the read request, and output the received data to the host; and
a cache memory size controller configured to control a size of an area assigned for prefetching data in the cache memory, based on a size of the data stored in the cache memory and a precalculated size of the data corresponding to the read request,
wherein the size of the area assigned for prefetching data in the cache memory represents a) a size of remaining data excluding the data corresponding to the read request and b) the precalculated size of the data corresponding to the read request, and
wherein the cache memory size controller determines whether the size of the data stored in the cache memory is greater than a predetermined size whenever data corresponding to each of a plurality of read requests of the host is provided from the cache memory to the host in response to the plurality of read requests, and decreases the size of the area in the cache memory when a result obtained by determining that the size of the data stored in the cache memory is greater than the predetermined size successively occurs a predetermined number of times or more.