| CPC G06F 11/1044 (2013.01) [G06F 12/0806 (2013.01); G06F 2212/1032 (2013.01)] | 7 Claims |
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1. A semiconductor memory device configured to execute a mask write process for rewriting data having a data length smaller than a preset data access unit, comprising:
a plurality of banks including
a data recording unit in which rewritten data is to be written, and
an error check and correct (ECC) code recording unit in which an error correction code corresponding to the rewritten data is to be written;
a sense amplifier disposed in each of the plurality of banks and configured to read and write data from and to each of the plurality of banks;
an ECC code generation unit configured to generate the error correction code;
an error correction unit configured to correct an error of data using the error correction code;
a first bus connecting the sense amplifier in each of the plurality of banks and the error correction unit and configured to transmit data output from the sense amplifier to the error correction unit; and
a second bus connecting the ECC code generation unit and the sense amplifier in each of the plurality of banks and configured to transmit data output from the ECC code generation unit to the sense amplifier,
wherein
the first bus and the second bus are separately provided so that an output of the data from the sense amplifier to the error correction unit via the first bus and an input of the data from the ECC code generation unit to the sense amplifier via the second bus are executable in parallel in a same bank among the plurality of banks.
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