US 12,493,514 B2
Apparatus and methods for memory fault detection within die architectures
Sateeshkumar Injarapu, Bangalore (IN); Manish Kumar Saxena, Bangalore (IN); Amit Duggal, Bangalore (IN); and Nitin Jaiswal, Bangalore (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2023, as Appl. No. 18/473,108.
Prior Publication US 2025/0103420 A1, Mar. 27, 2025
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/0784 (2013.01); G06F 11/102 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory controller die package comprising:
a data memory device;
decoder logic circuitry communicatively and electrically coupled to the data memory device, the decoder logic circuitry configured to:
receive a plurality of data words from the data memory device;
receive a first error correcting code (ECC) for each of the plurality of data words from an ECC memory device coupled to the decoder logic circuitry;
generate, for each of the plurality of data words, a second error correcting code based on a corresponding one of the plurality of data words;
generate, for each of the plurality of data words, an error signature based on the first error correcting code and the second error correcting code corresponding to each of the plurality of data words;
error generation logic circuitry communicatively and electrically coupled to the decoder logic circuitry, the error generation logic circuitry configured to:
generate a single error status based on the error signatures for the plurality of data words, the single error status indicating a consolidated error for the plurality of data words; and
ECC logging logic circuitry communicatively and electrically coupled to the error generation logic circuitry, ECC logging logic circuitry configured to:
generate and transmit an error signal based on the single error status to at least one component electrically coupled to the memory controller die package.