US 12,493,469 B1
Microprocessor that extends sequential multi-fetch block macro-op cache entries
John G Favor, San Francisco, CA (US); and Michael N. Michael, Folsom, CA (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on Apr. 24, 2024, as Appl. No. 18/645,269.
Application 18/645,269 is a continuation in part of application No. 18/380,152, filed on Oct. 13, 2023, granted, now 12,282,430.
Application 18/645,269 is a continuation in part of application No. 18/380,150, filed on Oct. 13, 2023, granted, now 12,299,449.
Application 18/380,152 is a continuation in part of application No. 18/240,249, filed on Aug. 30, 2023, granted, now 12,253,951.
Application 18/380,152 is a continuation in part of application No. 18/240,249, filed on Aug. 30, 2023, granted, now 12,253,951.
Claims priority of provisional application 63/547,230, filed on Nov. 3, 2023.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3806 (2013.01) [G06F 9/30181 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, wherein a FBlk comprises a sequential run of architectural instructions;
a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), wherein a ME holds MOPs into which architectural instructions of one or more FBlks are decoded, wherein a MOP comprises an instruction executable by an execution unit of the microprocessor; and
a fusion engine;
wherein an ME comprises:
training fields that indicate whether the ME and another ME appear as a consistent sequence in the program instruction stream; and
an indication of whether the ME is either:
a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk whose architectural instructions have been decoded into the MOPs of the SF-ME, or
a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks whose architectural instructions have been decoded into the MOPs of the MF-ME;
wherein the PRU is configured to:
update the training fields of each ME in the MOC that the PRU predicts is in the program instruction stream;
instruct the fusion engine to build in the MOC a first MF-ME using the MOPs of a first set of two or more MEs when the training fields of the first set of MEs indicate the first set of MEs appear as a first consistent sequence within the program instruction stream;
continue updating the training fields; and
instruct the fusion engine to build in the MOC a second MF-ME using the MOPs of the first MF-ME and a third ME when the training fields of the first MF-ME indicate the first MF-ME and the third ME appear as a second consistent sequence within the program instruction stream.