US 12,493,467 B1
Control register for storing instruction size information
Omer Lichter, Tel Aviv (IL); Alon Yaakov, Raanana (IL); and Nadav Malki, Ashod (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 5, 2024, as Appl. No. 18/734,464.
Int. Cl. G06F 9/30 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/30123 (2013.01) [G06F 9/30069 (2013.01); G06F 9/4812 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor circuit including:
a plurality of register circuits; and
an event handler circuit configured to:
detect a processing event that causes the processor circuit to halt execution of a current instruction and transfer control to a kernel;
in response to a detection of the processing event:
store a program counter value corresponding to the current instruction in a counter register circuit of the plurality of register circuits;
store information indicative of a cause of the processing event in a type register circuit of the plurality of register circuits; and
store a size of the current instruction in a size register circuit of the plurality of register circuits.