| CPC G06F 3/0604 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0689 (2013.01)] | 20 Claims |

|
1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
the at least one processing device being configured:
to receive in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system;
to store the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system; and
to control processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system;
wherein the first and second input-output timeout values comprise respective first and second host-side input-output timeout values, and wherein controlling processing of the input-output operations based at least in part on the corresponding input-output timeout values comprises establishing in the storage system respective first and second storage-side instances of the first and second host-side input-output timeout values for use in the storage system.
|