US 12,493,317 B2
Clock management circuit and clock management method
Yu-Jie Liang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Aug. 22, 2023, as Appl. No. 18/236,713.
Claims priority of application No. 111132085 (TW), filed on Aug. 25, 2022.
Prior Publication US 2024/0069590 A1, Feb. 29, 2024
Int. Cl. G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) 10 Claims
OG exemplary drawing
 
1. A clock management circuit for managing an operating clock of a processor circuit, the processor circuit changing a level of a state signal according to an interrupt, the clock management circuit comprising:
a delay circuit configured to delay a wake-up interrupt to generate a delayed wake-up interrupt; and
a clock control circuit coupled to the delay circuit and configured to generate the operating clock according to a reference clock, generate the wake-up interrupt according to the state signal, and adjust a frequency of the operating clock according to the delayed wake-up interrupt.