US 11,839,091 B2
Three-dimensional semiconductor memory device
Junhyoung Kim, Seoul (KR); Kwang-Soo Kim, Hwaseong-si (KR); Bonghyun Choi, Yongin-si (KR); and Siwan Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 3, 2020, as Appl. No. 17/011,156.
Application 17/011,156 is a division of application No. 16/403,795, filed on May 6, 2019, granted, now 10,840,252.
Claims priority of application No. 10-2018-0101549 (KR), filed on Aug. 28, 2018.
Prior Publication US 2020/0402983 A1, Dec. 24, 2020
Int. Cl. H10B 43/20 (2023.01); H10B 69/00 (2023.01)
CPC H10B 69/00 (2023.02) [H10B 43/20 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a first connection region arranged in a first direction; and
a first block structure on the substrate, the first block structure including:
a cell array portion on the cell array region;
a first connecting portion on the first connection region and adjacent to the cell array portion in the first direction; and
a second connecting portion on the first connection region and adjacent to the first connecting portion in a second direction crossing the first direction,
wherein:
the second connecting portion is symmetric with respect to the first connecting portion in a plan view and has a height difference from the first connecting portion in a side view,
the first connecting portion includes first electrodes, which are vertically stacked to form an upward staircase structure in the second direction,
the second connecting portion includes second electrodes, which are vertically stacked to form an upward staircase structure in a direction opposite to the second direction, and
a topmost step of the upward staircase structure of the second connecting portion is lower than a bottommost step of the upward staircase structure of the first connecting portion.