US 11,838,668 B2
Photoelectric conversion device
Taichi Kasugai, Kanagawa (JP); and Shintaro Takenaka, Kanagawa (JP)
Assigned to CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Apr. 26, 2022, as Appl. No. 17/729,731.
Claims priority of application No. 2021-076563 (JP), filed on Apr. 28, 2021.
Prior Publication US 2022/0353450 A1, Nov. 3, 2022
Int. Cl. H04N 25/768 (2023.01); H04N 25/767 (2023.01); H04N 25/772 (2023.01)
CPC H04N 25/768 (2023.01) [H04N 25/767 (2023.01); H04N 25/772 (2023.01)] 14 Claims
OG exemplary drawing
 
1. A photoelectric conversion device comprising:
a pixel unit in which a plurality of pixels each including three or more photoelectric converters, a floating diffusion to which charges of the plurality of photoelectric converters are transferred, and an output unit that outputs a signal corresponding to a voltage of the floating diffusion are arranged so as to form a plurality of rows and a plurality of columns;
a vertical scanning unit that performs a readout processing for reading out a signal of the pixel and a reset processing for resetting the pixel on the plurality of pixels arranged in the pixel unit while switching the photoelectric converter to be processed and the floating diffusion to be processed; and
a control unit configured to control the vertical scanning unit,
wherein the control unit includes a readout row address generation unit that generates a row address of a pixel from which a signal is readout during the readout processing and outputs the row address to the vertical scanning unit, and a reset row address generation unit that generates a row address of a pixel to be reset during the reset processing and outputs the row address to the vertical scanning unit,
wherein a first cycle, which is a cycle in which the photoelectric converter to be processed is switched during the readout processing and the reset processing, is shorter than a second cycle, which is a cycle in which the floating diffusion to be processed is switched during the readout processing and the reset processing,
wherein each of an update cycle of the row address in the readout row address generation unit and an update cycle of the row address in the reset row address generation unit is equal to the second cycle, and
wherein each of a setting unit of an update timing of the row address in the readout row address generation unit and a setting unit of an update timing of the row address in the reset row address generation unit is equal to a length of one cycle of the first cycle.