US 11,838,411 B2
Permutation cipher encryption for processor-accelerator memory mapped input/output communication
Santosh Ghosh, Hillsboro, OR (US); Luis Kida, Beaverton, OR (US); and Reshma Lal, Hillsboro, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 20, 2022, as Appl. No. 18/068,663.
Application 18/068,663 is a continuation of application No. 17/342,267, filed on Jun. 8, 2021, abandoned.
Prior Publication US 2023/0117518 A1, Apr. 20, 2023
Int. Cl. H04L 9/08 (2006.01); H04L 9/06 (2006.01)
CPC H04L 9/088 (2013.01) [H04L 9/0618 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first permutation pipeline to defuse a count and a key into a permutation state;
a first exclusive-OR (XOR) to generate ciphertext data from 64-bits of the permutation state and plaintext data;
a concatenator to concatenate the plaintext data and additional authenticated data (AAD) to produce a concatenation result;
a second XOR to generate an XOR result from the concatenation result and the permutation state; and
a second permutation pipeline to generate an authentication tag of the XOR result and the key.