US 11,838,402 B2
Ultra low power core for lightweight encryption
Emre Salman, Albany, NY (US); Milutin Stanacevic, Albany, NY (US); Yasha Karimi, Albany, NY (US); Tutu Wan, Albany, NY (US); and Yuanfei Huang, Albany, NY (US)
Assigned to The Research Foundation for The State University of New York, Albany, NY (US)
Appl. No. 17/438,662
Filed by The Research Foundation for The State University of New York, Albany, NY (US)
PCT Filed Mar. 13, 2020, PCT No. PCT/US2020/022522
§ 371(c)(1), (2) Date Sep. 13, 2021,
PCT Pub. No. WO2020/186125, PCT Pub. Date Sep. 17, 2020.
Claims priority of provisional application 62/817,631, filed on Mar. 13, 2019.
Prior Publication US 2022/0158819 A1, May 19, 2022
Int. Cl. H04L 9/06 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/0625 (2013.01) [H04L 9/0819 (2013.01); H04L 9/0618 (2013.01); H04L 2209/24 (2013.01); H04L 2209/805 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing unit comprising:
a SIMON block cipher for transforming plaintext input data into encrypted output data using one or more encryption keys, including
a key expansion module for generating and outputting the one or more encryption keys, and including a first series of adiabatic registers for holding key generation data values, and for using adiabatic switching to transmit the key generation data values through the first series of adiabatic registers to generate the one or more encryption keys; and
a round function module for receiving the plaintext input data and the one or more encryption keys, for encrypting the plaintext input data, in one or more rounds using the one or more encryption keys, to generate the encrypted data, and for outputting the encrypted data, and including a second series of adiabatic registers for holding encryption data, and for using adiabatic switching to transmit the encryption data through the second series of adiabatic registers to generate the encrypted output data.