US 11,838,398 B2
Semiconductor device
Hyeonju Lee, Suwon-si (KR); Jiyoung Kim, Suwon-si (KR); Jaehyun Park, Seoul (KR); Seuk Son, Suwon-si (KR); Sooeun Lee, Suwon-si (KR); and Dongchul Choi, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 31, 2022, as Appl. No. 18/051,138.
Claims priority of application No. 10-2021-0165215 (KR), filed on Nov. 26, 2021.
Prior Publication US 2023/0170891 A1, Jun. 1, 2023
Int. Cl. H04L 7/033 (2006.01); H03K 3/037 (2006.01); H03K 5/26 (2006.01); H03K 5/00 (2006.01)
CPC H04L 7/033 (2013.01) [H03K 3/037 (2013.01); H03K 5/26 (2013.01); H03K 2005/00286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
processing circuitry configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, greater than the first frequency, and to output data for a time corresponding to a unit interval of the data signal,
the processing circuitry configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, and to output a plurality of pieces of error data for the time corresponding to the unit interval, and
the processing circuitry configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.