CPC H04L 7/0016 (2013.01) [H04L 7/0004 (2013.01); H04L 7/0079 (2013.01)] | 19 Claims |
13. A system comprising:
a sync signal generator configured to generate and transmit a synchronization signal for synchronization of a plurality of processing elements; and
a plurality of synchronizers, wherein each processing element of the plurality of processing elements includes a respective synchronizer of the plurality of synchronizers, each of the plurality of synchronizers being configured to count from different count values until a predetermined end count sequence value in response to receiving the synchronization signal, the plurality of synchronizers being configured to cause respective processing elements of the plurality of processing elements to start a respective function or operation in response to a respective synchronizer reaching the predetermined end count sequence value, the plurality of synchronizers include first and second upstream synchronizers and a downstream synchronizer, and wherein the different count values include a first count value and a second count value, the first count value being representative of a difference in time between the first upstream synchronizer receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal, and the second count value being representative of a difference in time between the second upstream synchronizer receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal.
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