US 11,837,653 B2
Lateral bipolar junction transistor including a stress layer and method
Jagar Singh, Clifton Park, NY (US); Alexander M. Derrickson, Saratoga Springs, NY (US); Alvin J. Joseph, Williston, VT (US); Andreas Knorr, Saratoga Springs, NY (US); and Judson R. Holt, Ballston Lake, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Dec. 20, 2021, as Appl. No. 17/555,561.
Claims priority of provisional application 63/238,242, filed on Aug. 30, 2021.
Prior Publication US 2023/0065785 A1, Mar. 2, 2023
Int. Cl. H01L 29/73 (2006.01); H01L 29/737 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/737 (2013.01) [H01L 29/0821 (2013.01); H01L 29/1008 (2013.01); H01L 29/6625 (2013.01); H01L 29/66242 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A structure comprising:
a transistor comprising: a base; a collector; and an emitter, wherein the base has sidewall spacers on opposing sidewalls and is positioned laterally between the collector and the emitter; and
a first dielectric layer partially covering the transistor, wherein the first dielectric layer is above at least one of the sidewall spacers, and has one end above the transistor between the collector and the emitter, and wherein the first dielectric layer completely covers the collector and at least partially covers the base.