US 11,837,648 B2
Stacked thin film transistors with nanowires
Seung Hoon Sung, Portland, OR (US); Abhishek A. Sharma, Portland, OR (US); Van H. Le, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 15, 2022, as Appl. No. 17/695,744.
Application 17/695,744 is a continuation of application No. 16/650,153, granted, now 11,309,400, previously published as PCT/US2018/013570, filed on Jan. 12, 2018.
Prior Publication US 2022/0208991 A1, Jun. 30, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66439 (2013.01) [H01L 27/1225 (2013.01); H01L 29/0669 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a body including an oxide semiconductor material including first, second, and
third portions, the second portion between the first and third portions, the
first portion being a source region and the third portion being a drain region, wherein at least one of the first portion or the third portion of the body includes a damaged surface having a higher concentration of oxygen vacancies relative to the second portion;
a gate dielectric structure wrapped around the second portion of the body; and
a gate electrode structure wrapped around the gate dielectric structure, the gate
electrode structure comprising metal.