US 11,837,607 B2
Display device, display module, and electronic device
Shunpei Yamazaki, Tokyo (JP); Kenichi Okazaki, Tochigi (JP); Daisuke Kurosaki, Tochigi (JP); Yasutaka Nakazawa, Tochigi (JP); Kazunori Watanabe, Tokyo (JP); and Koji Kusunoki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 14, 2022, as Appl. No. 17/944,275.
Application 17/944,275 is a continuation of application No. 16/999,237, filed on Aug. 21, 2020, granted, now 11,456,320.
Application 16/999,237 is a continuation of application No. 15/820,965, filed on Nov. 22, 2017, granted, now 10,756,118, issued on Aug. 25, 2020.
Claims priority of application No. 2016-233560 (JP), filed on Nov. 30, 2016; and application No. 2017-099002 (JP), filed on May 18, 2017.
Prior Publication US 2023/0014200 A1, Jan. 19, 2023
Int. Cl. G02F 1/1368 (2006.01); H01L 27/12 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/1229 (2013.01) [G02F 1/1368 (2013.01); G06F 3/0446 (2019.05); G06F 3/04166 (2019.05); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel comprising a first transistor and a pixel electrode;
a signal line;
a scan line; and
a driver circuit comprising a second transistor,
wherein the signal line and the scan line are electrically connected to the first transistor,
wherein the driver circuit is configured to output a signal to the scan line,
wherein the first transistor and the second transistor each comprises an oxide semiconductor in a channel formation region,
wherein one of a source electrode and a drain electrode of the first transistor comprises an oxide layer,
wherein the other of the source electrode and the drain electrode of the first transistor comprises a metal layer,
wherein the pixel electrode is in contact with the one of the source electrode and the drain electrode of the first transistor,
wherein in a plan view, the signal line is arranged to extend in a first direction,
wherein in the plan view, the scan line is arranged to extend in a second direction intersecting with the first direction,
wherein in the plan view, the signal line comprises a region intersecting with the scan line,
wherein in the plan view, a width of the intersecting region in the second direction is smaller than a width of a region of the signal line not intersecting with the scan line,
wherein in the plan view, the oxide layer comprises a first region and a second region,
wherein a width of the first region in the second direction is smaller than a width of the second region in the second direction,
wherein in the plan view, the second region overlaps with the pixel electrode,
wherein in the plan view, the second region overlaps with a conductive layer comprising a material same as a gate electrode of the first transistor, and
wherein the conductive layer and the second region are configured to form a capacitor.